US 12,218,010 B2
Vertical field-effect transistor devices having gate liner
Hwi Chan Jun, Yongin-si (KR); and Min Gyu Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 22, 2024, as Appl. No. 18/418,795.
Application 18/418,795 is a continuation of application No. 17/669,452, filed on Feb. 11, 2022, granted, now 11,915,982.
Application 17/669,452 is a continuation of application No. 17/035,857, filed on Sep. 29, 2020, granted, now 11,282,752, issued on Mar. 22, 2022.
Claims priority of provisional application 62/970,278, filed on Feb. 5, 2020.
Prior Publication US 2024/0170338 A1, May 23, 2024
Int. Cl. H01L 21/8234 (2006.01); H01L 29/792 (2006.01)
CPC H01L 21/823487 (2013.01) [H01L 21/823437 (2013.01); H01L 21/823481 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a first vertical field-effect transistor (VFET) and a second VFET on a substrate, wherein
each of the first VFET and the second VFET comprises a bottom source/drain region in the substrate, a channel region, and a top source/drain region that are sequentially stacked on the substrate in a vertical direction, and a gate structure on a side surface of the channel region, and
wherein the first VFET comprises a first side surface facing the second VFET, and the second VFET comprises a first side surface facing the first VFET;
a gate liner comprises a first gate liner continuously extending from the first side surface of the first VFET onto the first side surface of the second VFET, and a second gate liner continuously extending from a second side surface of the first VFET onto an upper surface of the substrate, wherein the second side surface of the first VFET is opposite to the first side surface of the first VFET;
a first gap capping layer that is between the first side surface of the first VFET and the first side surface of the second VFET and comprises opposing side surfaces contacting the first gate liner;
a transistor isolation layer that is on the second gate liner and is spaced apart from the second gate liner; and
a second gap capping layer that is adjacent to an upper surface of the transistor isolation layer and contacts the second gate liner and the transistor isolation layer,
wherein the first gate liner and the first gap capping layer enclose a first cavity, and
the second gate liner, the second gap capping layer, and the transistor isolation layer enclose at least a portion of a second cavity.