US 12,218,007 B2
Self-aligned via formation using spacers
Yi-Nien Su, Hsinchu (TW); and Jyu-Horng Shieh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 7, 2021, as Appl. No. 17/340,629.
Claims priority of provisional application 63/085,209, filed on Sep. 30, 2020.
Prior Publication US 2022/0102212 A1, Mar. 31, 2022
Int. Cl. H01L 21/76 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 21/76897 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first mandrel and a second mandrel over a dielectric layer;
forming a first spacer and a second spacer on the first mandrel and the second mandrel, respectively, wherein the first spacer and the second spacer are next to each other with a first space in between;
forming a protection layer covering a part of the first mandrel and the first spacer;
forming a patterned etching mask over the protection layer, wherein the protection layer and the patterned etching mask are formed of different materials;
etching the dielectric layer to form an opening in the dielectric layer, wherein in the etching, the first mandrel, the second mandrel, the protection layer, the first spacer, the second spacer, and the patterned etching mask collectively define patterns of the dielectric layer, wherein the opening is overlapped by the first space;
filling a conductive material into the opening; and
performing a planarization process on the conductive material.