US 12,218,006 B2
System, device and methods of manufacture
Chen-Hua Yu, Hsinchu (TW); Wei Ling Chang, Hsinchu (TW); Chuei-Tang Wang, Taichung (TW); Tin-Hao Kuo, Hsinchu (TW); and Che-Wei Hsu, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 7, 2023, as Appl. No. 18/503,453.
Application 18/503,453 is a continuation of application No. 17/870,075, filed on Jul. 21, 2022, granted, now 11,848,235.
Application 17/870,075 is a continuation of application No. 16/926,107, filed on Jul. 10, 2020, granted, now 11,404,316, issued on Aug. 2, 2022.
Claims priority of provisional application 62/954,286, filed on Dec. 27, 2019.
Prior Publication US 2024/0071825 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/77 (2017.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 25/18 (2023.01); H01L 23/40 (2006.01)
CPC H01L 21/76895 (2013.01) [H01L 21/76898 (2013.01); H01L 21/77 (2013.01); H01L 23/528 (2013.01); H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 25/18 (2013.01); H01L 23/4006 (2013.01); H01L 2023/4087 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/06182 (2013.01); H01L 2224/16145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a plurality of semiconductor dies at least partially within a semiconductor substrate;
forming a first local interconnect adjacent to a first side of the semiconductor substrate, wherein the first local interconnect electrically couples a first semiconductor die of the plurality of semiconductor dies to a second semiconductor die of the plurality of semiconductor dies, the first local interconnect passing across a scribe region disposed between the first semiconductor die and the second semiconductor die; and
forming an integrated fan-out structure adjacent to a second side of the semiconductor substrate opposite the first side, wherein the integrated fan-out structure electrically couples a third semiconductor die of the plurality of semiconductor dies to the first semiconductor die of the plurality of semiconductor dies.