US 12,218,005 B2
Integrated circuit device
Hsia-Wei Chen, Taipei (TW); Fu-Ting Sung, Taoyuan (TW); Yu-Wen Liao, New Taipei (TW); Wen-Ting Chu, Kaohsiung (TW); Fa-Shen Jiang, Taoyuan (TW); and Tzu-Hsuan Yeh, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 25, 2024, as Appl. No. 18/422,726.
Application 18/422,726 is a continuation of application No. 17/141,852, filed on Jan. 5, 2021, granted, now 11,894,267.
Prior Publication US 2024/0162088 A1, May 16, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76877 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76832 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
an interconnect layer comprising a first conductive feature and a second conductive feature;
a memory structure over and in contact with the first conductive feature, wherein the memory structure comprises at least a resistance switching element over the first conductive feature;
a third conductive feature over and in contact with the second conductive feature, wherein the third conductive feature comprises a first conductive line; and
a fourth conductive feature over and in contact with the memory structure, wherein the fourth conductive feature comprises a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.