US 12,217,999 B2
Trench isolation process
Chung-Lei Chen, Hsinchu (TW); Cheng-Hsin Chen, Toufen (TW); Chung Chieh Ting, Taipei (TW); Che-Yi Lin, Hsinchu (TW); and Clark Lee, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/818,497.
Application 17/818,497 is a continuation of application No. 16/949,214, filed on Oct. 20, 2020, granted, now 11,443,976.
Prior Publication US 2022/0392799 A1, Dec. 8, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 21/02123 (2013.01); H01L 21/30625 (2013.01); H01L 21/31133 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of providing trench isolation, comprising:
performing a deep trench isolation process for a silicon wafer;
forming, after performing the deep trench isolation process, a shallow trench having a lower surface that is above a lower surface of a deep trench associated with the deep trench isolation process,
wherein an entirety of a first portion of the lower surface of the shallow trench resides below an entirety of a second portion of the lower surface of the shallow trench and is co-planar with a top surface of an entirety of the deep trench; and
depositing an insulating material within the shallow trench,
wherein a thickness of a first portion of the insulating material that is laterally displaced from the deep trench is greater than a thickness of a second portion of the insulating material that is above the deep trench.