	US 12,217,975 B2
	Semiconductor device having metal gate and poly gate
Alexander Kalnitsky, San Francisco, CA (US); Wei-Cheng Wu, Hsinchu County (TW); and Harry-Hak-Lay Chuang, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Dec. 1, 2023, as Appl. No. 18/527,151.
Application 17/850,643 is a division of application No. 16/796,667, filed on Feb. 20, 2020, granted, now 11,387,114, issued on Jul. 12, 2022.
Application 18/527,151 is a continuation of application No. 17/850,643, filed on Jun. 27, 2022, granted, now 11,854,828.
Claims priority of provisional application 62/865,833, filed on Jun. 24, 2019.
Prior Publication US 2024/0096643 A1, Mar. 21, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 21/321 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)

CPC H01L 21/3212 (2013.01) [H01L 21/82345 (2013.01); H01L 27/088 (2013.01); H01L 29/4916 (2013.01); H01L 29/66545 (2013.01); H01L 29/66681 (2013.01); H01L 29/6681 (2013.01); H01L 29/7816 (2013.01)]

20 Claims

1. A method of fabricating a semiconductor device, comprising:

forming shallow trench isolation (STI) structures in a substrate;

forming a dummy gate stack and a poly gate stack over the substrate, wherein the dummy gate stack has a lateral dimension wider than a lateral dimension of the poly gate stack;

forming a source region between the dummy gate stack and a first one of the STI structures;

forming a drain region between the poly gate stack and a second one of the STI structures;

after forming the drain region between the poly gate stack and the second one of the STI structures, conformally depositing an oxide material layer over the substrate, the dummy gate stack and the poly gate stack;

patterning the oxide material layer; and

replacing the dummy gate stack with a metal gate stack, wherein the metal gate stack has a lateral dimension wider than the lateral dimension of the poly gate stack.