US 12,217,913 B2
Chip parts
Keisuke Fukae, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Sep. 22, 2022, as Appl. No. 17/950,592.
Claims priority of application No. 2021-160038 (JP), filed on Sep. 29, 2021.
Prior Publication US 2023/0102250 A1, Mar. 30, 2023
Int. Cl. H01G 4/232 (2006.01); H01G 4/008 (2006.01); H01G 4/224 (2006.01); H01G 4/30 (2006.01); H01L 49/02 (2006.01)
CPC H01G 4/232 (2013.01) [H01G 4/008 (2013.01); H01G 4/224 (2013.01); H01G 4/30 (2013.01); H01L 28/60 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A chip part, comprising:
a substrate, having a first main surface and a second main surface opposite to the first main surface;
a capacitor portion, disposed on the first main surface of the substrate when viewed from a plan view and along a normal direction of the first main surface, wherein the capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on the first main surface;
a substrate body portion, formed around the capacitor portion using a portion of the substrate and at least connected to one of an end portion and another end portion of the plurality of wall portions in the lengthwise direction;
a lower electrode, disposed along top and side surfaces of the plurality of wall portions;
a capacitive film, disposed on the lower electrode along the top and side surfaces of the plurality of wall portions;
an upper electrode, disposed on the capacitive film;
a first external electrode, disposed on the first main surface of the substrate and electrically connected to the lower electrode; and
a second external electrode, separated from the first external electrode on the first main surface of the substrate and electrically connected to the upper electrode;
wherein the plurality of wall portions are formed of a plurality of pillar units,
each of the plurality of pillar units includes a central portion and three protruding portions extending from the central portion to three mutually different directions in the plan view,
the plurality of wall portions are formed by connecting the protruding portions of adjacent pillar units, and
the capacitor portion, in the plan view, includes:
a first capacitor portion, including the plurality of wall portions having the lengthwise direction as a first lengthwise direction; and
a second capacitor portion, including the plurality of wall portions having the lengthwise direction as a second lengthwise direction different from the first lengthwise direction, and
wherein
the lower electrode includes a first contact region formed on an outer side of the capacitor portion and surrounding the capacitor portion,
the upper electrode includes a second contact region overlapping the capacitor portion in the plan view, and
the chip part further includes:
a first electrode film, disposed on the first main surface of the substrate and electrically connecting the first contact region to the first external electrode; and
a second electrode film, disposed on the first main surface of the substrate and electrically connecting the second contact region to the second external electrode, and
the substrate includes a semiconductor substrate,
a base region of first conductivity type is formed on the first main surface of the semiconductor substrate and overlapping the first external electrode and the second external electrode in the plan view, and
the chip part further includes:
a first diode, including an impurity region of second conductivity type formed in the base region below the first external electrode and connected to the first electrode film; and
a second diode, including another impurity region of second conductivity type formed in the base region below the second external electrode and connected to the second electrode film.