US 12,217,826 B2
Memory array test structure and method of forming the same
Meng-Han Lin, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 16, 2024, as Appl. No. 18/443,997.
Application 18/302,560 is a division of application No. 17/397,414, filed on Aug. 9, 2021, granted, now 11,657,863, issued on May 23, 2023.
Application 18/443,997 is a continuation of application No. 18/302,560, filed on Apr. 18, 2023, granted, now 11,935,624.
Claims priority of provisional application 63/211,765, filed on Jun. 17, 2021.
Prior Publication US 2024/0194234 A1, Jun. 13, 2024
Int. Cl. G11C 8/08 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01); G11C 29/50 (2006.01); H01L 21/822 (2006.01)
CPC G11C 8/08 (2013.01) [G11C 29/025 (2013.01); G11C 29/12 (2013.01); G11C 29/50 (2013.01); H01L 21/8221 (2013.01); G11C 2029/1202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a memory array, including:
N horizontal planes of memory cells, where N is two or greater, each Nth plane being vertically above the (N−1) plane, each horizontal plane including a plurality of word lines, each word line of each horizontal plane having a first end and a second end separated from the first end by a distance in a first horizontal direction, wherein the distance in an Nth horizontal plane is less is less than the distance in the (N−1) horizontal plane;
at first transistor in each of the N horizontal planes, each first transistor being between adjacent ones of the word lines in the same horizontal plane, each first transistor in the Nth plane being vertically stacked above a respective first transistor in the (N−1) horizontal plane;
a second transistor in each of the N horizontal planes, each second transistor being between adjacent ones of the word lines in the same horizontal plane, each second transistor in an Nth plane being vertically stacked above a respective second transistor in the (N−1) plane, each second transistor being electrically isolated from a respective first transistor by a vertically extending dielectric feature;
a first source line electrically connecting respective sources of the respective first transistors in the N horizontal planes, and a vertically extending second source line electrically connecting respective sources of the respective second transistors in the N horizontal planes; and
an interconnect structure, including:
N sets of first conductive vias, respective first conductive vias of the Nth set contacting respective first ends of respective word lines of the Nth horizontal plane of the memory array; and
N sets of second conductive vias, respective second conductive vias of the Nth set contacting respective second ends of respective word lines of the Nth horizontal plane of the memory array.