	US 12,217,823 B2
	Memory device for supporting command bus training mode and method of operating the same
Young-hun Kim, Yongin-si (KR); Si-hong Kim, Hwaseong-si (KR); Tae-young Oh, Seoul (KR); and Kyung-soo Ha, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 9, 2023, as Appl. No. 18/332,325.
Application 18/332,325 is a continuation of application No. 17/518,888, filed on Nov. 4, 2021, granted, now 11,715,504.
Application 17/518,888 is a continuation of application No. 16/946,217, filed on Jun. 10, 2020, granted, now 11,195,566, issued on Dec. 7, 2021.
Application 16/946,217 is a continuation of application No. 16/196,777, filed on Nov. 20, 2018, granted, now 10,720,197, issued on Jul. 21, 2020.
Claims priority of provisional application 62/734,347, filed on Sep. 21, 2018.
Claims priority of application No. 10-2017-0155812 (KR), filed on Nov. 21, 2017; and application No. 10-2018-0111604 (KR), filed on Sep. 18, 2018.
Prior Publication US 2023/0317128 A1, Oct. 5, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 8/18 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01)

CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1066 (2013.01); G11C 7/1084 (2013.01); G11C 7/1093 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/50012 (2013.01); G11C 7/1072 (2013.01); G11C 2207/2254 (2013.01); G11C 2207/2272 (2013.01)]

11 Claims

1. A method of operating a memory device, the method comprising:

receiving a clock signal through a clock terminal;

receiving a data clock signal through a data clock terminal;

receiving a frequency set point (FSP) change command through a command/address (CA) bus, an operating frequency of the memory device being switched based on the FSP change command;

receiving a first data signal through a first data terminal;

detecting a logic level of the first data signal at one of a rising edge and a falling edge of the data clock signal, and entering into a command bus training (CBT) mode upon detecting a first logic level of the first data signal; and

switching parameters of FSP operation settings based on the FSP change command during the CBT mode,

wherein the parameters of the FSP operation settings includes a first FSP operation mode signal representing a low frequency setting in a normal mode, a second FSP operation mode signal representing an intermediate frequency setting in the normal mode, and a third FSP operation mode signal representing a high frequency setting in the normal mode.