US 12,217,822 B2
Memory device with source line control
Perng-Fei Yuh, Hsinchu (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/232,542.
Application 18/232,542 is a continuation of application No. 17/584,127, filed on Jan. 25, 2022, granted, now 11,776,595.
Prior Publication US 2023/0386536 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 11/16 (2006.01); G11C 11/407 (2006.01); G11C 17/18 (2006.01)
CPC G11C 7/1096 (2013.01) [G11C 7/1069 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/165 (2013.01); G11C 11/407 (2013.01); G11C 17/18 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory cell comprising a select transistor corresponding to a bit line and a word line; and
a memory controller coupled to the memory cell, the memory controller to:
apply a first write voltage to the bit line during a first time period to write data to the memory cell; and
apply a second write voltage to the word line coupled to the memory cell during the first time period,
wherein a difference between the first write voltage and the second write voltage is less than an allowable stress voltage of the select transistor, wherein the second write voltage is between the first write voltage and a third write voltage of a source line coupled to the memory cell.