US 12,217,821 B2
Storage device and operating method with multiple channels
Seung Han Ryu, Gyeonggi-do (KR); In Bo Shim, Gyeonggi-do (KR); Hyeong Rak Kim, Gyeonggi-do (KR); and Hae Seong Jeong, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 3, 2022, as Appl. No. 17/831,969.
Claims priority of application No. 10-2022-0010798 (KR), filed on Jan. 25, 2022.
Prior Publication US 2023/0238040 A1, Jul. 27, 2023
Int. Cl. G11C 7/10 (2006.01)
CPC G11C 7/1087 (2013.01) [G11C 7/109 (2013.01); G11C 7/1093 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A storage device comprising:
a memory device including a plurality of memory dies and a plurality of interfaces connected to the plurality of memory dies; and
a memory controller configured to:
address a memory die among the plurality of memory dies by providing the memory device with an address value comprising a two bit combination of a logical value of an address latch enable (ALE) signal and a logical value of a command latch enable (CLE) signal, and
control the memory device such that the memory die performs a memory operation,
wherein the memory controller addresses the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a logical value of a chip enable (CE) signal,
wherein the logical value of the address latch enable (ALE) signal and the logical value of the command latch enable (CLE) signal are input to the plurality of interfaces during predetermined N cycles, where N is a natural number.