US 12,217,819 B2
Computing device, memory controller, and method for performing an in-memory computation
Yu-Der Chih, Hsinchu (TW); and Chia-Fu Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 25, 2022, as Appl. No. 17/656,425.
Claims priority of provisional application 63/229,814, filed on Aug. 5, 2021.
Prior Publication US 2023/0045840 A1, Feb. 16, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/4074 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for performing an in-memory computation, comprising:
storing data in a plurality of memory cells of a memory array, the data comprising a plurality of weights for computation;
determining whether an update command to change at least one of the plurality of weights is received;
in response to receiving the update command, performing a write operation on the memory array to update the changed weight; and
disabling the write operation on the memory array until receiving a next update command to change at least one of the plurality of weights;
wherein the update command is outputted when one of the plurality of weights is to be replaced with a different weight before the write operation is performed.