US 12,217,818 B2
Bias generation circuit and memory circuit
Zhonglai Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 16, 2023, as Appl. No. 18/154,937.
Application 18/154,937 is a continuation of application No. PCT/CN2022/099536, filed on Jun. 17, 2022.
Claims priority of application No. 202210238528.7 (CN), filed on Mar. 11, 2022.
Prior Publication US 2023/0290385 A1, Sep. 14, 2023
Int. Cl. G11C 29/00 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01)
CPC G11C 5/146 (2013.01) [G11C 5/147 (2013.01); G11C 7/1084 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bias generation circuit, comprising:
a first load circuit coupled between a working voltage and a regulating node;
a bias circuit configured to receive the working voltage and output a bias voltage according to the working voltage;
a voltage stabilizing circuit which is coupled to an output end of the bias circuit and configured to receive a reference voltage and regulate a voltage of the regulating node according to the bias voltage and the reference voltage; and
a second load circuit having one end coupled to the output end of the bias circuit and the other end coupled to the regulating node.