US 12,217,817 B2
Memory device and method of forming the same
Jung-Piao Chiu, Kaohsiung (TW); and Yu-Sheng Chen, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 20, 2023, as Appl. No. 18/356,204.
Application 18/356,204 is a continuation of application No. 17/387,924, filed on Jul. 28, 2021, granted, now 11,763,857.
Claims priority of provisional application 63/188,476, filed on May 14, 2021.
Prior Publication US 2023/0368819 A1, Nov. 16, 2023
Int. Cl. G11C 5/06 (2006.01); H01L 25/065 (2023.01); H10B 63/10 (2023.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC G11C 5/063 (2013.01) [H01L 25/0652 (2013.01); H10B 63/10 (2023.02); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/821 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array comprising:
first-tier word lines extending in a first direction;
second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction; and
bit lines extending in a third direction angularly offset from the first and second directions, and the bit lines being arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.