CPC G11C 5/063 (2013.01) [H01L 25/0652 (2013.01); H10B 63/10 (2023.02); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H10B 63/84 (2023.02); H10N 70/011 (2023.02); H10N 70/821 (2023.02)] | 20 Claims |
1. A memory device, comprising:
a memory cell array comprising:
first-tier word lines extending in a first direction;
second-tier word lines disposed below the first-tier word lines and extending in a second direction angularly offset from the first direction; and
bit lines extending in a third direction angularly offset from the first and second directions, and the bit lines being arranged between a pair of the first-tier word lines and between a pair of the second-tier word lines.
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