US 12,217,816 B2
Semiconductor wiring device and method
Hidenori Yamaguchi, Higashihiroshima (JP); and Keizo Kawakita, Higashi Hiroshima (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/823,173.
Prior Publication US 2024/0071425 A1, Feb. 29, 2024
Int. Cl. G11C 5/00 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 16/06 (2006.01); H10B 43/35 (2023.01)
CPC G11C 5/06 (2013.01) [G11C 7/1006 (2013.01); G11C 16/06 (2013.01); H10B 43/35 (2023.02)] 17 Claims
OG exemplary drawing
 
13. A method, comprising:
forming a first transmission line on a semiconductor substrate;
forming a dielectric over the first transmission line;
using a trench mask to lithographically form a trench in the dielectric for a second transmission line above the first transmission line;
using a via mask to lithographically form a via opening in the dielectric, wherein a via mask footprint and a trench mask footprint overlap in an intersection region smaller than either the via mask or the trench mask, and wherein the via opening is dimensioned by the intersection region; and
filling the trench and via opening in a single conductor deposition operation.