US 12,217,815 B2
Memory testing system and memory testing method
Chien Yu Chen, New Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Nov. 16, 2022, as Appl. No. 18/055,847.
Prior Publication US 2024/0161857 A1, May 16, 2024
Int. Cl. G11C 29/46 (2006.01); G11C 29/12 (2006.01); G11C 29/36 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/12005 (2013.01); G11C 29/36 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory testing system, comprising:
at least one memory device;
a power supply configured to provide a first reference voltage to the at least one memory device according to a control signal; and
a processor configured to:
provide the control signal to control the power supply to vary the first reference voltage among a plurality of voltage levels; and
test the at least one memory device under the plurality of voltage levels to generate a plurality of first testing results corresponding to the plurality of voltage levels,
wherein the processor is further configured to execute a first testing program and control the power supply to vary the first reference voltage from a first voltage level of the plurality of voltage levels to a second voltage level of the plurality of voltage levels to generate the plurality of first testing results corresponding to the first testing program, and
execute a second testing program different from the first testing program and control the power supply to vary the first reference voltage from the first voltage level to the second voltage level to generate a plurality of second testing results corresponding to the second testing program,
wherein the first voltage level is one of a lowest one of the plurality of voltage levels and a highest one of the plurality of voltage levels, and
the second voltage level is another one of the lowest one of the plurality of voltage levels and the highest one of the plurality of voltage levels.