CPC G11C 29/42 (2013.01) [G11C 7/065 (2013.01); G11C 11/40611 (2013.01); G11C 29/20 (2013.01); G11C 29/44 (2013.01); G11C 2029/1202 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a memory array comprising a plurality of word lines, wherein each of the plurality of word lines comprises a plurality of count value memory cells configured to store a plurality of values each representing a number of activations of a corresponding one of the plurality of word lines;
a count control circuit configured to receive a value of the plurality of values from the plurality of count value memory cells of a word line of the plurality of word lines when the word line is activated, compare the value to a threshold value and activate a trigger signal when the value is equal to or greater than the threshold value; and
a refresh control circuit configured to latch a current row address and perform a targeted refresh operation when the active trigger signal is received.
|