US 12,217,811 B2
Programmable logic device with design for test functionality
Ket Chong Yap, San Jose, CA (US); Chihhung Liao, Fremont, CA (US); and Shieh Huan Yen, New Taipei (TW)
Assigned to QuickLogic Corporation, San Jose, CA (US)
Filed by QuickLogic Corporation, San Jose, CA (US)
Filed on Nov. 7, 2023, as Appl. No. 18/504,078.
Application 18/504,078 is a continuation of application No. 17/714,136, filed on Apr. 5, 2022, granted, now 11,848,066.
Prior Publication US 2024/0170087 A1, May 23, 2024
Int. Cl. G11C 29/32 (2006.01); G11C 29/12 (2006.01); G11C 29/20 (2006.01); H03K 19/173 (2006.01); H03K 19/17728 (2020.01)
CPC G11C 29/32 (2013.01) [G11C 29/1201 (2013.01); G11C 29/20 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/3202 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A programmable logic device (PLD) comprising:
a scan enable input, wherein, when the scan enable input is asserted, the PLD enters a shift mode; and
at least one first logic block section, wherein the at least one first logic block section comprises:
a first configurable memory bit coupled to a scan chain in the shift mode;
a first multiplexer (MUX) with a first select input directly coupled to the first configurable memory bit; and
a configurable look up table (LUT) including:
a first plurality of configurable memory bits coupled in series along the scan chain in the shift mode and coupled to the first configurable memory bit; and
a plurality of MUXes, the plurality of MUXes being coupled to each of the first plurality of configurable memory bits and to an output of the first MUX.