US 12,217,810 B2
Memory readout circuit and method
Chih-Min Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 11, 2024, as Appl. No. 18/601,100.
Application 18/601,100 is a continuation of application No. 18/190,796, filed on Mar. 27, 2023, granted, now 11,929,128.
Application 18/190,796 is a continuation of application No. 17/671,372, filed on Feb. 14, 2022, granted, now 11,615,860, issued on Mar. 28, 2023.
Application 17/671,372 is a continuation of application No. 17/028,837, filed on Sep. 22, 2020, granted, now 11,270,780, issued on Mar. 8, 2022.
Claims priority of provisional application 63/002,550, filed on Mar. 31, 2020.
Prior Publication US 2024/0212771 A1, Jun. 27, 2024
Int. Cl. G11C 17/18 (2006.01); G11C 11/16 (2006.01); G11C 17/16 (2006.01)
CPC G11C 17/18 (2013.01) [G11C 11/1673 (2013.01); G11C 17/16 (2013.01); G11C 11/161 (2013.01); G11C 11/1659 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a plurality of anti-fuse cells coupled to a first selection circuit;
a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit;
an amplifier comprising a first input terminal coupled to each of the first and second selection circuits;
an analog-to-digital converter (ADC) comprising input terminals coupled to output terminals of the amplifier; and
a comparator comprising a first input port coupled to an output port of the ADC,
wherein the amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to:
current levels received from the first selection circuit at the first input terminal of the amplifier, and
first voltage levels received from the second selection circuit at the first input terminal of the amplifier.