US 12,217,809 B2
One-time programmable bitcell for frontside and backside power interconnect
Andrew Edward Horch, Seattle, WA (US)
Assigned to SYNOPSYS, INC., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Sunnyvale, CA (US)
Filed on Nov. 29, 2022, as Appl. No. 18/071,321.
Claims priority of provisional application 63/290,022, filed on Dec. 15, 2021.
Prior Publication US 2023/0187003 A1, Jun. 15, 2023
Int. Cl. G11C 16/24 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01)
CPC G11C 17/16 (2013.01) [G11C 17/18 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A bitcell of a one-time programmable memory comprising:
a write-once programmable circuit element and a node connected in series between a word line and a power rail;
a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending substantially parallel to the word line; and
a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending substantially parallel to the bitline.