Assigned to NEO Semiconductor, Inc., San Jose, CA (US)
Filed by NEO Semiconductor, Inc., San Jose, CA (US)
Filed on Aug. 1, 2022, as Appl. No. 17/816,720.
Application 17/816,720 is a continuation in part of application No. 17/492,553, filed on Oct. 1, 2021.
Application 17/492,553 is a continuation in part of application No. 17/446,165, filed on Aug. 26, 2021.
Application 17/446,165 is a continuation in part of application No. 17/330,304, filed on May 25, 2021.
Application 17/330,304 is a continuation of application No. 16/849,875, filed on Apr. 15, 2020, granted, now 11,049,579, issued on Jun. 29, 2021.
Application 16/849,875 is a continuation in part of application No. 16/687,556, filed on Nov. 18, 2019, granted, now 11,056,190, issued on Jul. 6, 2021.
Claims priority of provisional application 63/349,571, filed on Jun. 6, 2022.
Claims priority of provisional application 63/116,159, filed on Nov. 19, 2020.
Claims priority of provisional application 63/112,038, filed on Nov. 10, 2020.
Claims priority of provisional application 63/107,386, filed on Oct. 29, 2020.
Claims priority of provisional application 63/105,877, filed on Oct. 27, 2020.
Claims priority of provisional application 63/104,305, filed on Oct. 22, 2020.
Claims priority of provisional application 63/094,343, filed on Oct. 20, 2020.
Claims priority of provisional application 63/091,895, filed on Oct. 14, 2020.
Claims priority of provisional application 63/090,171, filed on Oct. 9, 2020.
Claims priority of provisional application 63/086,543, filed on Oct. 1, 2020.
Claims priority of provisional application 63/070,266, filed on Aug. 26, 2020.
Claims priority of provisional application 62/884,139, filed on Aug. 7, 2019.
Claims priority of provisional application 62/871,198, filed on Jul. 7, 2019.
Claims priority of provisional application 62/848,567, filed on May 15, 2019.
Claims priority of provisional application 62/843,556, filed on May 5, 2019.
Claims priority of provisional application 62/799,669, filed on Jan. 31, 2019.
Claims priority of provisional application 62/783,199, filed on Dec. 20, 2018.
Claims priority of provisional application 62/774,128, filed on Nov. 30, 2018.
Claims priority of provisional application 62/770,150, filed on Nov. 20, 2018.
Claims priority of provisional application 62/768,979, filed on Nov. 18, 2018.
Prior Publication US 2023/0022531 A1, Jan. 26, 2023
1. A method for programming a memory device having a plurality of memory chips wherein each chip has multiple-level-cells, the method comprising:
loading first data in a first chip;
programming the first data into selected cells of the first chip using a single-level-cell (SLC) programming mode;
reprogramming the first data stored in the selected cells of the first chip to other cells of the first chip using a multiple-level-cell programming mode;
repeating the operations of loading, programming, and reprogramming for the remaining chips;
wherein the loading operations for the remaining chips begin at the completion of the loading operation for the first chip and occur in a non-overlapping sequential manner; and
wherein the loading operations for the remaining chips are performed in parallel with the programming and reprogramming operations of the first chip.
