US 12,217,807 B2
Non-volatile memory device and programming method thereof
Yonghyuk Choi, Suwon-si (KR); and Yohan Lee, Incheon (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 5, 2022, as Appl. No. 17/960,346.
Claims priority of application No. 10-2021-0162599 (KR), filed on Nov. 23, 2021.
Prior Publication US 2023/0162807 A1, May 25, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); G11C 11/5628 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An operating method of a non-volatile memory device that comprises a plurality of cell strings each comprising a first stack and a second stack adjacent to the first stack, the operating method comprising:
performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage comprising a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, each program loop of the plurality of program loops comprising a bit line setup period and a program execution period;
applying, during the time period, second voltages comprising a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings; and
maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings, such that the third voltage applied to the non-select word line connected to the second stack of each of the plurality of cell strings is maintained at the first level over multiple bit line setup periods and multiple program execution periods of the plurality of program loops.