US 12,217,804 B2
Nonvolatile memory device including combined sensing node and cache read method thereof
Yongsung Cho, Suwon-si (KR); Min-Hwi Kim, Suwon-si (KR); and Hosang Cho, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 5, 2022, as Appl. No. 17/960,630.
Claims priority of application No. 10-2022-0007354 (KR), filed on Jan. 18, 2022; and application No. 10-2022-0054806 (KR), filed on May 3, 2022.
Prior Publication US 2023/0230640 A1, Jul. 20, 2023
Int. Cl. G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cache read method of a nonvolatile memory device including a memory cell array, a plurality of page buffer units, and cache latches, each of the plurality of page buffer units having a sensing latch and a sensing node line, the method comprising:
performing a first on-chip valley search (OVS) read on a selected memory cell using a first sensing node line and a first sensing latch of a first page buffer unit of the plurality of page buffer units;
storing, during a program suspend period, first data sensed from the selected memory cell in the first sensing latch, the first data based on a result of the first OVS read;
transferring the first data to sensing node lines of at least one page buffer unit, from a remainder of the plurality of page buffer units; and
performing a second OVS read on the selected memory cell using the first sensing latch,
wherein, during the program suspend period, the plurality of page buffer units are occupied by write data of a suspended program operation.