US 12,217,801 B2
Bias voltage schemes during pre-programming and programming phases
Vinh Q. Diep, Hayward, CA (US); Yingda Dong, Los Altos, CA (US); and Ching-Huang Lu, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 7, 2022, as Appl. No. 18/076,537.
Claims priority of provisional application 63/292,052, filed on Dec. 21, 2021.
Prior Publication US 2023/0197164 A1, Jun. 22, 2023
Int. Cl. G11C 16/12 (2006.01); G11C 16/08 (2006.01); G11C 16/28 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/12 (2013.01) [G11C 16/08 (2013.01); G11C 16/28 (2013.01); G11C 16/30 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
causing, by a processing device, a first bias voltage with respect to a first dummy wordline of a set of dummy wordlines of a memory array to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, wherein the first dummy wordline is adjacent to a select gate of the memory array;
maintaining, by the processing device, the first bias voltage at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase, wherein the first bias voltage is ramped from the power supply voltage to the first dummy wordline seed voltage; and
causing, by a processing device during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a program inhibit bias voltage.