US 12,217,800 B2
Semiconductor device and data storage system including the same
Jaeho Ahn, Suwon-si (KR); Jiwon Kim, Suwon-si (KR); Sungmin Hwang, Suwon-si (KR); Joonsung Lim, Suwon-si (KR); and Sukkang Sung, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 29, 2024, as Appl. No. 18/591,728.
Application 18/591,728 is a continuation of application No. 17/523,337, filed on Nov. 10, 2021, granted, now 11,935,597.
Claims priority of application No. 10-2020-0155461 (KR), filed on Nov. 19, 2020.
Prior Publication US 2024/0249775 A1, Jul. 25, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 23/48 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC G11C 16/10 (2013.01) [G11C 16/26 (2013.01); H01L 23/481 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first chip structure; and
a second chip structure on the first chip structure and including a memory cell array region,
wherein the first chip structure includes:
a semiconductor substrate having a first surface and a second surface opposing each other;
a back side insulating layer below the second surface of the semiconductor substrate;
an external input/output conductive pattern below the back side insulating layer;
a first active region on the first surface of the semiconductor substrate;
an isolation layer on the first surface of the semiconductor substrate and a side surface of the first active region;
a transistor including a source/drain region within a first portion of the first active region and a gate structure on a second portion of the first active region;
an interlayer insulating layer on the first active region and the isolation layer;
an input/output connection wiring on the interlayer insulating layer;
a first input/output contact plug penetrating through the interlayer insulating layer and electrically connected to the input/output connection wiring; and
a through-electrode structure penetrating through the semiconductor substrate and the back side insulating layer and electrically connected to the first input/output contact plug and the external input/output conductive pattern,
wherein the through-electrode structure includes a through-electrode and an insulating spacer on a side surface of the through-electrode,
wherein an upper end of the through-electrode is at a higher level than an upper end of the insulating spacer, and
wherein the through-electrode contacts the first input/output contact plug.