CPC G11C 16/08 (2013.01) [G11C 16/0433 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array comprising a block having a plurality of wordlines, a plurality of bitlines, and a plurality of strings, each string of the plurality of strings being connected to a respective bitline of the plurality of bitlines, wherein the block is divided into a plurality of sub-blocks comprising a first sub-block and a second sub-block, wherein each sub-block of the plurality of sub-blocks comprises a respective set of strings of the plurality of strings, and wherein each string of the set of strings is located at a sub-block position within its respective sub-block; and
control logic, operatively coupled with the memory array, to perform operations comprising:
selecting each sub-block of the plurality of sub-blocks;
causing a first voltage to be applied to a dummy wordline of the plurality of wordlines, wherein the first voltage activates a first set of dummy cells associated with the dummy wordline and having a first state and deactivates a second set of cells associated with the dummy wordline and having a second state different from the first state, wherein each sub-block of the plurality of sub-blocks comprises a single string of the set of strings corresponding to an open string connected to a respective dummy cell of the first set of dummy cells and remaining strings of the set of strings each corresponding to a closed string connected to a respective dummy cell of the second set of dummy cells, and wherein the open string of the first sub-block is located at a different sub-block position than the open string of the second sub-block; and
causing a second voltage to be applied to a selected wordline of the plurality of wordlines, wherein the second voltage causes data to be read out from each open string to a respective page buffer of a plurality of page buffers.
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