US 12,217,798 B2
Bank design with differential bulk bias in eFuse array
Meng-Sheng Chang, Chubei (TW); and Chia-En Huang, Xinfeng Township (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,198.
Application 18/362,198 is a continuation of application No. 17/448,486, filed on Sep. 22, 2021, granted, now 11,756,622.
Claims priority of provisional application 63/175,699, filed on Apr. 16, 2021.
Prior Publication US 2023/0377654 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 17/18 (2006.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 17/16 (2006.01); H10B 20/25 (2023.01)
CPC G11C 16/0483 (2013.01) [G11C 16/12 (2013.01); G11C 17/165 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a plurality of memory cells, each of the plurality of memory cells including a resistor and a transistor coupled to each other in series; and
a sensing circuit including a read access transistor coupled to each of the plurality of memory cells, wherein respective bulk ports of the transistors of at least a first memory cell and a second memory cell of the plurality of memory cells are biased at different voltage levels, wherein, in response to the read access transistor receiving a read bit line voltage, the sensing circuit is configured to sense at least one of the first memory cell or the second memory cell.