US 12,217,796 B2
Sequence alignment with memory arrays
Justin Eno, Boise, ID (US); Sean S. Eilert, Boise, ID (US); Ameen D. Akel, Boise, ID (US); and Kenneth M. Curewitz, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/931,277.
Prior Publication US 2024/0087643 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); C12Q 1/6869 (2018.01); G11C 7/16 (2006.01); G16B 30/10 (2019.01)
CPC G11C 13/0069 (2013.01) [C12Q 1/6869 (2013.01); G11C 7/16 (2013.01); G11C 13/004 (2013.01); G16B 30/10 (2019.02)] 21 Claims
OG exemplary drawing
 
1. A method comprising:
programming a plurality of resistance values to a plurality of memory cells, wherein the plurality of resistance values correspond to nucleotide types;
providing a plurality of voltage values to a plurality of access lines coupled to the plurality of memory cells, wherein the plurality of voltage values correspond to the nucleotide types;
summing a plurality of currents along corresponding ones of a plurality of sense lines coupled to the plurality of memory cells, wherein the plurality of currents are functions of the plurality of voltage values and corresponding ones of the plurality of resistance values of the plurality of memory cells along corresponding ones of the plurality of sense lines,
providing a plurality of outputs based, at least in part, on the summing; and
comparing the plurality of outputs to a target value.