US 12,217,795 B2
Memory and operating method thereof
Meng-Fan Chang, Taichung (TW); and Yen-Cheng Chiu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed on Mar. 4, 2024, as Appl. No. 18/595,188.
Application 18/595,188 is a continuation of application No. 17/705,306, filed on Mar. 26, 2022, granted, now 11,996,147.
Claims priority of provisional application 63/227,888, filed on Jul. 30, 2021.
Prior Publication US 2024/0203491 A1, Jun. 20, 2024
Int. Cl. G11C 7/08 (2006.01); G11C 13/00 (2006.01); H03K 19/20 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0004 (2013.01); G11C 7/08 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a memory device configured to store a plurality of bits;
a first switch coupled to the memory device at a first node;
a second switch configured to control the first switch; and
a feedback device configured to adjust the second switch based on a first voltage signal generated at the first node,
wherein each of the first switch and the second switch is configured to receive a reference voltage signal, and
the first voltage signal is generated based on the plurality of bits.