| CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4093 (2013.01); G11C 11/4094 (2013.01)] | 20 Claims |

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1. A data transfer circuit in a nonvolatile memory device, the data transfer circuit comprising:
a plurality of first repeaters connected to a first circuit element disposed in a data input/output (I/O) path of the nonvolatile memory device;
a plurality of second repeaters connected to a second circuit element disposed in the data I/O path of the nonvolatile memory device, the second circuit element being spaced apart from the first circuit element; and
a plurality of signal lines configured to connect the plurality of first repeaters and the plurality of second repeaters, the plurality of signal lines including a first group of signal lines and a second group of signal lines which are alternatingly arranged,
wherein the plurality of first repeaters include:
a first group of repeaters that are activated in a first operation mode; and
a second group of repeaters that are activated in a second operation mode having a non-overlapping operating interval with the first operation mode,
wherein the plurality of second repeaters include:
a third group of repeaters that are activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines; and
a fourth group of repeaters that are activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines,
wherein the second group of signal lines are floated in the first operation mode, and
wherein the first group of signal lines are floated in the second operation mode.
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