US 12,217,792 B2
Memory circuit and method of operating same
Atul Katoch, Hsinchu (TW); and Sahil Preet Singh, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on May 13, 2022, as Appl. No. 17/744,428.
Claims priority of provisional application 63/267,453, filed on Feb. 2, 2022.
Prior Publication US 2023/0245694 A1, Aug. 3, 2023
Int. Cl. G11C 11/4096 (2006.01); G11C 11/4076 (2006.01); G11C 11/4091 (2006.01); G11C 11/4094 (2006.01); G11C 11/4099 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4076 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/4099 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
a set of memory cells configured to store data; and
a local input output (LIO) circuit coupled to a global bit line and the set of memory cells, the LIO circuit comprising:
a sense amplifier configured to sense a first signal in response to at least a sense amplifier signal, the first signal corresponding to a value of the data stored in the set of memory cells;
a driver circuit configured to generate a global bit line signal in response to at least the first signal or an inverted first signal; and
a booster circuit coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal, wherein the booster circuit comprises:
a first inverter configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal coupled to the global bit line, and a first output terminal;
a delay circuit coupled to the first output terminal of the first inverter, and configured to generate a delayed second signal in response to the second signal; and
a second inverter configured to generate a third signal in response to the delayed second signal, the second inverter including a second input terminal and a second output terminal, the second input terminal being coupled to an output terminal of the delay circuit, the third signal corresponds to the delayed global bit line signal.