| CPC G11C 11/4093 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01)] | 20 Claims |
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1. A non-volatile memory device, comprising:
one or more memory blocks including
a plurality of memory cells connected to a plurality of word lines, and
a plurality of memory cell strings arranged in rows and columns;
a page buffer unit including a plurality of page buffers connected to the plurality of memory cell strings, respectively;
one or more pass units including a plurality of pass transistors that are configured to supply operation voltages to the plurality of word lines;
one or more monitoring units including one or more monitoring pass transistors connected to the plurality of pass transistors;
a voltage generator that is configured to supply activation voltages to a first pass transistor, in which a leakage current is to be measured, from among the plurality of pass transistors, and to the one or more monitoring pass transistors; and
a control logic that is configured to
control the voltage generator to generate the activation voltages by using a voltage control signal, and
detect the leakage current based on monitoring voltages output from the one or more monitoring pass transistors.
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