US 12,217,789 B2
Control amplification circuit, sensitive amplifier and semiconductor memory
Daoxun Wu, Hefei (CN); and Weibing Shang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 20, 2022, as Appl. No. 17/844,259.
Application 17/844,259 is a continuation of application No. PCT/CN2022/079712, filed on Mar. 8, 2022.
Claims priority of application No. 202111663568.8 (CN), filed on Dec. 31, 2021.
Prior Publication US 2023/0215491 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 11/4091 (2006.01)
CPC G11C 11/4091 (2013.01) 20 Claims
OG exemplary drawing
 
1. A control amplification circuit, comprising:
a power consumption control circuit, configured to receive a power consumption control signal and output a first reference signal according to the power consumption control signal;
an isolating circuit, configured to determine a control instruction signal and generate an isolation control signal according to the control instruction signal; and
an amplification circuit, configured to receive the first reference signal, the isolation control signal and a signal to be processed, and process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal.