US 12,217,787 B2
Apparatus, system and method to detect and improve an input clock performance of a memory device
Arvind A. Kumar, Palo Alto, CA (US); James Alexander McCall, Portland, OR (US); Bill H. Nale, Livermore, CA (US); John R. Goles, Folsom, CA (US); and Dean-Dexter R. Eugenio, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,854.
Prior Publication US 2021/0312972 A1, Oct. 7, 2021
Int. Cl. G06F 1/12 (2006.01); G06F 1/08 (2006.01); G06F 13/16 (2006.01); G11C 11/4072 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 13/1689 (2013.01); G11C 11/4072 (2013.01); G11C 11/4074 (2013.01); G11C 11/4093 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An integrated circuit of a memory subsystem including:
an input and output (I/O) interface to connect to a memory device;
one or more processors coupled to the I/O interface and configured to:
perform one or more training iterations to tune a target clock signal frequency to be applied at the memory device, each of the one or more training iterations including:
causing a modified clock signal frequency to be applied at the memory device; and
decoding a quality feedback message from the memory device including an indication of a performance of the clock signal frequency at the memory device; and
in response to a determination that the performance of the clock signal frequency falls within a target performance range of the memory device and that the clock signal frequency is below the target clock signal frequency, perform a subsequent training iteration of the one or more training iterations, and otherwise cause application at the memory device, during a memory operation, of a highest clock signal frequency corresponding to a training iteration for which performance of the clock signal was within the target performance range.