US 12,217,785 B2
Method of and apparatus for refreshing memory devices
Ming-Yen Chuang, Hsinchu (TW); and Katherine H. Chiang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 27, 2023, as Appl. No. 18/160,564.
Claims priority of provisional application 63/376,883, filed on Sep. 23, 2022.
Prior Publication US 2024/0105249 A1, Mar. 28, 2024
Int. Cl. G11C 11/406 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/4091 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
an array of word lines;
a first array of memory cells configured to receive selection signals from the array of word lines, wherein each memory cell is configured to become a selected memory cell based on the selection signals;
a first set of data lines associated with the first array of memory cells, wherein each memory cell in the first array of memory cells is connected to one or more data lines in the first set of data lines; and
a first read-write driver connected to the first set of data lines and configured to receive a flip-refresh control signal, wherein the first read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in the selected memory cell, and wherein the first read-write driver is configured to store a second bit value into the selected memory cell through the first set of data lines based on the first bit value, with the second bit value being a bit inversion of the stored bit value.