a base substrate, comprising a display area and a bezel area on at least one side of the display area;

a plurality of pixel units in the display area, wherein the plurality of pixel units are arranged on the base substrate in an array along a row direction and a column direction, and each pixel unit comprises a plurality of sub-pixels;

a plurality of scanning signal lines arranged on the base substrate, wherein the plurality of scanning signal lines are configured to provide a scanning signal to a plurality of rows of sub-pixels, respectively;

a gate driver circuit arranged on the base substrate and located in the bezel area, wherein the gate driver circuit is configured to the output scanning signal;

a plurality of load compensation units arranged on the base substrate and located in the bezel area, wherein the plurality of load compensation units are between the gate driver circuit and the plurality of pixel units; and

a plurality of scanning signal lead wires arranged on the base substrate and located in the bezel area, wherein the plurality of scanning signal lead wires are configured to transmit the scanning signal output by the gate driver circuit to the plurality of scanning signal lines, respectively,

wherein at least one load compensation unit comprises a compensation capacitor comprising a first compensation capacitor electrode in a first conductive layer and a second compensation capacitor electrode in a semiconductor layer, and an orthographic projection of the first compensation capacitor electrode on the base substrate at least partially overlaps with an orthographic projection of the second compensation capacitor electrode on the base substrate;

wherein the first conductive layer is on a side of the semiconductor layer away from the base substrate, and the first compensation capacitor electrode is electrically connected to the scanning signal lead wire;

wherein the scanning signal lines and the scanning signal lead wires are in the first conductive layer, and the first compensation capacitor electrode and the scanning signal lead wire that are electrically connected to each other are formed into a continuously extending integral structure;

wherein the display substrate further comprises a first voltage signal lead wire in a second conductive layer, the second conductive layer is on a side of the first conductive layer away from the base substrate; and the second compensation capacitor electrode is electrically connected to the first voltage signal lead wire; and

wherein the display substrate further comprises a first conductive connection portion in the second conductive layer, the first conductive connection portion extends from the first voltage signal lead wire towards the display area, and the first conductive connection portion is electrically connected to the second compensation capacitor electrode through a plurality of first via holes.