CPC G09G 3/3611 (2013.01) [G02F 1/133603 (2013.01); G02F 1/133612 (2021.01); G09G 2310/0243 (2013.01); G09G 2330/00 (2013.01); H01L 25/167 (2013.01)] | 18 Claims |
1. A driver circuit, comprising a logic control component and a plurality of pins coupled to the logic control component;
wherein the plurality of pins include:
a clock pin configured to receive a clock signal;
a data pin configured to receive, under control of the logic control component, a data signal in a period of an active level of the clock signal; and
at least two output pins;
the logic control component is configured to generate a driving control signal corresponding to each output pin according to the data signal, so as to control an electrical signal flowing through the output pin;
wherein the data signal includes address information and luminance information; the driver circuit is configured with address information;
the logic control component is further configured to:
compare the address information in the data signal with the address information of the driver circuit, and,
in a case where the address information in the data signal matches the address information of the driver circuit, acquire the luminance information in the data signal, and generate the driving control signal according to the luminance information in the data signal.
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