US 12,217,708 B2
Display device
Ji Seon Lee, Hwaseong-si (KR); Jin Sung An, Seongnam-si (KR); Seok Je Seong, Seongnam-si (KR); Seong Jun Lee, Seoul (KR); and Se Wan Son, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-do (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Dec. 15, 2023, as Appl. No. 18/541,885.
Application 18/541,885 is a continuation of application No. 18/093,515, filed on Jan. 5, 2023, granted, now 11,881,181.
Application 18/093,515 is a continuation of application No. 17/680,964, filed on Feb. 25, 2022, granted, now 11,580,916, issued on Feb. 14, 2023.
Application 17/680,964 is a continuation of application No. 17/193,281, filed on Mar. 5, 2021, granted, now 11,302,268, issued on Apr. 12, 2022.
Claims priority of application No. 10-2020-0028624 (KR), filed on Mar. 6, 2020.
Prior Publication US 2024/0119907 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3291 (2016.01); H01L 27/12 (2006.01); H10K 59/121 (2023.01)
CPC G09G 3/3291 (2013.01) [G09G 2300/0426 (2013.01); H10K 59/1213 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display device, comprising:
a substrate;
a first transistor disposed above the substrate and including:
a first active pattern covered by a first gate insulating layer; and
a first gate electrode covered by a first interlayer insulating layer disposed between the first gate insulating layer and the first interlayer insulating layer, wherein the first transistor generates a driving current;
a second transistor disposed above the first gate electrode and including:
a second active pattern covered by a second gate insulating layer; and
a second gate electrode covered by a second interlayer insulating layer disposed between the second gate insulating layer and the second interlayer insulating layer, wherein a first end of the second active pattern is electrically connected to a first end of the first active pattern, and a second end of the second active pattern is electrically connected to the first gate electrode of the first transistor;
a first connecting pattern disposed above the second active pattern and connected to the first gate electrode; and
a second connecting pattern disposed above the first connecting pattern and connected to the first connecting pattern and the second end of the second active pattern.