| CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0233 (2013.01)] | 15 Claims |
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1. A display panel, comprising: a display region and a non-display region that at least partially surrounds the display region; wherein,
the display region comprises: M first display regions sequentially disposed along a first direction, a first display region comprises a plurality of first signal lines sequentially disposed along the first direction and extending along a second direction, the second direction intersects with the first direction;
the non-display region comprises M first gate driver on array (GOA) circuits and M clock signal line groups, a clock signal line group comprises a plurality of clock signal lines, and the at least two clock signal lines are respectively located in at least two clock signal line groups of the M clock signal line groups; a first gate driver on array circuit comprises a plurality of first gate driver on array units, a plurality of first gate driver on array units in an m-th first gate driver on array circuit are connected with at least one clock signal line of a plurality of clock signal lines of an m-th clock signal line group, and a plurality of first gate driver on array units in the m-th first gate driver on array circuit are connected with a plurality of first signal lines in an m-th first display region in one-to-one correspondence, wherein M is a positive integer greater than or equal to 2, and m is a positive integer less than or equal to M;
the M clock signal line groups respectively correspond to the M first display regions and the M first GOA circuits;
the M clock signal line groups comprise a first clock signal line group, a second clock signal line group, and a third clock signal line group, and the first clock signal line group comprises a first clock signal line and a second clock signal line, and the second clock signal line group comprises a third clock signal line and a fourth clock signal line, and the third clock signal line group comprises a fifth clock signal line and a sixth clock signal line;
the non-display region comprises a first first GOA circuit GOA circuit, a second first GOA circuit GOA circuit, a third first GOA circuit GOA circuit;
clock signal lines connected with first first GOA circuit are only the first clock signal line and the second clock signal line;
clock signal lines connected with second first GOA circuit are only the third clock signal line and the fourth clock signal line;
clock signal lines connected with third first GOA circuit are only the fifth clock signal line and the sixth clock signal line.
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