| CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] | 18 Claims |
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1. A scan driving circuit, comprising a plurality of shift registers and a plurality of clock signal lines; wherein
each shift register of the plurality of shift registers includes:
an input circuit,
a black frame insertion circuit,
an output circuit,
a scan input signal terminal,
a first clock signal terminal,
a black frame insertion input signal terminal,
a first voltage signal terminal,
a second clock signal terminal,
a third clock signal terminal,
a shift signal terminal,
a fourth clock signal terminal, and
a first output signal terminal;
the input circuit is electrically connected to the scan input signal terminal and a pull-up node;
the input circuit is configured to:
in response to a scan input signal received at the scan input signal terminal, transmit the scan input signal to the pull-up node;
the black frame insertion circuit is electrically connected to the first clock signal terminal, the black frame insertion input signal terminal, the first voltage signal terminal, the second clock signal terminal and the pull-up node;
the black frame insertion circuit is configured to, under control of a first clock signal transmitted by the first clock signal terminal, a black frame insertion input signal transmitted by the black frame insertion input signal terminal and a second clock signal transmitted by the second clock signal terminal, transmit the second clock signal to the pull-up node;
the output circuit is electrically connected to the pull-up node, the third clock signal terminal, the shift signal terminal, the fourth clock signal terminal and the first output signal terminal;
the output circuit is configured to:
transmit a third clock signal received at the third clock signal terminal to the shift signal terminal under control of a voltage of the pull-up node, and
transmit a fourth clock signal received at the fourth clock signal terminal to the first output signal terminal under the control of the voltage of the pull-up node;
wherein the plurality of shift registers include first shift registers and second shift registers;
a third clock signal terminal and a fourth clock signal terminal of each first shift register of the first shift registers are electrically connected to a same clock signal line; and
a third clock signal terminal and a fourth clock signal terminal of each second shift register of the second shift registers are electrically connected to different clock signal lines, respectively.
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