an underlayer substrate comprising a display area; and

a circuit structure layer, located in the display area, wherein:

the circuit structure layer comprises at least one first circuit area and at least one second circuit area;

the first circuit area comprises at least one first gate drive circuit; the second circuit area comprises at least one second gate drive circuit;

the first gate drive circuit is cascaded with the second gate drive circuit;

the first gate drive circuit comprises a plurality of cascaded first gate drive units, and the second gate drive circuit comprises a plurality of cascaded second gate drive units; the plurality of first gate drive units are sequentially arranged in a second direction, and the plurality of second gate drive units are sequentially arranged in the second direction;

the first circuit area and the second circuit area are misaligned in a first direction; the first direction is intersected with the second direction;

the circuit structure layer further comprises: a first connection line area; the first connection line area comprises at least one first signal line and at least one first connection line; the first signal line comprises at least one first sub-signal line and at least one second sub-signal line;

the first sub-signal line is electrically connected with the first gate drive circuit, and the second sub-signal line is electrically connected with the second gate drive circuit;

the first sub-signal line and the second sub-signal line are electrically connected by at least one first connection line, and the first connection line extends along the first direction;

the first connection area further comprises at least one first jumper line extending in the second direction; wherein the first jumper line is electrically connected with two first connection lines for transmitting a same signal; and

the first jumper line spans at least pixel circuits in two rows in the second direction.