US 12,217,679 B2
Display panel and display device
Yingteng Zhai, Xiamen (CN); Xiaoxiang He, Xiamen (CN); and Feng Qin, Shanghai (CN)
Assigned to TIANMA ADVANCED DISPLAY TECHNOLOGY INSTITUTE (XIAMEN) CO., LTD., Xiamen (CN)
Filed by TIANMA ADVANCED DISPLAY TECHNOLOGY INSTITUTE (XIAMEN) CO., LTD., Xiamen (CN)
Filed on May 24, 2023, as Appl. No. 18/322,606.
Claims priority of application No. 202310327763.6 (CN), filed on Mar. 30, 2023.
Prior Publication US 2023/0317009 A1, Oct. 5, 2023
Int. Cl. G09G 3/3233 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 2300/0426 (2013.01); G09G 2300/0814 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a pixel circuit and a light-emitting element, wherein the pixel circuit is configured to drive the light-emitting element to emit light; and
an initialization signal line configured to transmit an initialization signal; wherein
the initialization signal comprises an enabling level and a non-enabling level, and the enabling level of the initialization signal is configured to initialize a target node of the pixel circuit;
the initialization signal line extends in a first direction, and further comprises a first initialization signal line and a second initialization signal line; the pixel circuit comprises a plurality of first pixel circuits arranged in the first direction in a first pixel circuit row and a plurality of second pixel circuits arranged in the first direction in a second pixel circuit row; the first initialization signal line is electrically connected to the plurality of first pixel circuits in the first pixel circuit row, the second initialization signal line is electrically connected to the plurality of second pixel circuits in the second pixel circuit row; the first pixel circuit row and the second pixel circuit row are arranged in a second direction; wherein the first direction intersects with the second direction; and
a screen refresh cycle of the display panel comprises a first stage, wherein the first initialization signal line transmits the enabling level, and the second initialization signal line transmits the non-enabling level, in the first stage.