| CPC G09G 3/32 (2013.01) [G09G 2300/0439 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/08 (2013.01)] | 8 Claims |
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1. An electroluminescence display apparatus comprising:
a first pixel;
a second pixel disposed adjacent to the first pixel;
a shared data line electrically connected to both the first pixel and the second pixel, the shared data line configured to time-divisionally supply a first data voltage and a second data voltage;
a shared reference voltage line directly, electrically connected to both the first pixel and the second pixel, the shared reference voltage line configured to supply a reference voltage;
a first gate line electrically connected to the first pixel to transfer a first gate control signal;
a second gate line electrically connected to the first and second pixels in common to transfer a second gate control signal;
a third gate line electrically connected to the second pixel to transfer a third gate control signal; and
a gate driver electrically connected to the first, second, and third gate lines,
wherein each of the first and second gate lines has a first line width, and the third gate line has a second line width which differs from the first line width,
wherein the second gate line is commonly connected to a gate electrode of a first switching element in the first pixel and a gate electrode of a second switching element in the second pixel,
wherein the first switching element is electrically connected between a gate electrode of a first driving element of the first pixel and the shared data line,
wherein the second switching element is electrically connected between a source or a drain electrode of a second driving element of the second pixel and the shared reference voltage line,
wherein the gate driver is configured to:
generate the first gate control signal to supply the first gate control signal to the first gate line,
generate the second gate control signal to supply the second gate control signal to the second gate line, and
generate the third gate control signal to supply the third gate control signal to the third gate line,
wherein the shared data line supplies the first data voltage to the first pixel during a third period and supplies the second data voltage to the second pixel during a fourth period,
wherein a period when the third gate control signal has an on level overlaps with the third period and the fourth period, and
wherein a period when the first gate control signal has an on level does not overlap with the third period and the fourth period.
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