CPC G09G 3/001 (2013.01) [G09G 3/3607 (2013.01); G09G 2300/0452 (2013.01); G09G 2310/0262 (2013.01); G09G 2310/0281 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0297 (2013.01); G09G 2330/021 (2013.01); G09G 2340/00 (2013.01); G09G 2354/00 (2013.01); G09G 2370/00 (2013.01)] | 19 Claims |
1. A display panel, comprising:
a base substrate, comprising a display region and a peripheral region disposed outside the display region;
a plurality of data lines, located at a side of the base substrate, and extending from the display region to the peripheral region; wherein each of the plurality of data lines extends along a first direction, and the plurality of data lines are arranged along a second direction; and the first direction intersects with the second direction;
a plurality of scan lines, located at the side of the base substrate; wherein each of the plurality of scan lines extends along the second direction and the plurality of scan lines are arranged along the first direction;
a plurality of sub-pixels, respectively located at regions defined by the plurality of scan lines and the plurality of data lines; wherein at least two sub-pixels adjacent in the first direction and the second direction form a pixel island; and color of light emitted by any two adjacent sub-pixels in the second direction is identical;
a plurality of data selection control lines, arranged at the peripheral region and located at a same side of the base substrate as the plurality of data lines;
a plurality of data input lines, arranged at the peripheral region and locate at the same side of the base substrate as the plurality of data selection control lines; and
a plurality of data selection circuits, arranged at the peripheral and located at the same side of the base substrate as the plurality of data selection control lines;
wherein each data selection circuit comprises at least two selection switch groups;
wherein each selection switch group comprises: an input terminal, a plurality of control terminals, and a plurality of output terminals;
in wherein within each data selection circuit, each input terminal of different selection switch groups is coupled to a different data input line, each control terminal of different selection switch groups is coupled to a different data selection control line, and each i-th output terminal of different selection switch groups is coupled to a same data line, wherein, i is a positive integer;
wherein for each two adjacent data selection circuits, a left selection switch group within a first data selection circuit among the two adjacent data selection circuits and a right selection switch group within a second data selection circuit among the two adjacent data selection circuits are coupled to a same data input line; wherein the left selection switch group and the right selection switch group are connected with different data selection control lines;
and each of the plurality of data selection circuits is configured to: under control of signals of the plurality of data selection control lines, respectively provide a signal of a corresponding data input line to each coupled data line.
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