US 12,217,350 B2
Node encoding for spatially-organized ray tracing acceleration data structure
Ali Rabbani Rankouhi, St Albans (GB); Christopher A. Burns, Bushey (GB); Justin A. Hensley, Mountain View, CA (US); Luca Iuliano, Milton Keynes (GB); and Jonathan M. Redshaw, St Albans (GB)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 5, 2022, as Appl. No. 17/817,742.
Application 17/817,742 is a continuation of application No. 17/103,406, filed on Nov. 24, 2020, granted, now 11,436,784.
Claims priority of provisional application 63/058,868, filed on Jul. 30, 2020.
Prior Publication US 2022/0375155 A1, Nov. 24, 2022
Int. Cl. G06T 15/06 (2011.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 16/22 (2019.01); G06F 30/31 (2020.01); G06T 1/20 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01); G06T 17/00 (2006.01); G06Q 10/101 (2023.01); G06Q 50/04 (2012.01); G06T 17/10 (2006.01); G16H 40/67 (2018.01)
CPC G06T 15/06 (2013.01) [G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01); G06F 9/5027 (2013.01); G06F 16/2246 (2019.01); G06F 30/31 (2020.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 17/005 (2013.01); G06Q 10/101 (2013.01); G06Q 50/04 (2013.01); G06T 17/00 (2013.01); G06T 17/10 (2013.01); G06T 2210/12 (2013.01); G06T 2210/21 (2013.01); G16H 40/67 (2018.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
storage circuitry configured to store node data for a spatially organized acceleration data structure, including to store the following node information in a node data structure for a parent node:
origin coordinates for the node; and
child base address information that indicates a base address of a memory region within which data is stored for multiple child nodes of the parent node;
for a given child node of the multiple child nodes, child information that includes:
a field that indicates whether the child node is an interior node or a leaf node;
for an internal child node, quantized bounding region information for a bounding region corresponding to the child node, wherein the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates;
for a leaf child node:
a field that indicates a size of data for the leaf child node, wherein the spatially organized acceleration data structure supports leaf nodes of different sizes and the parent node includes multiple leaf child nodes having different sizes; and
a field that indicates an offset, within the memory region, at which the data for the leaf node is located, relative to the child base address;
traversal circuitry that includes bounding region tester circuitry, wherein the traversal circuitry is configured to:
traverse multiple nodes of the data structure; and
test, using the bounding region tester circuitry during the traversal, whether a ray intersects a bounding region indicated by a node of the data structure, wherein the testing is based on the node information for the node and ray information for the ray.