US 12,217,327 B2
Multi-tile graphics processing unit
Michal Mrozek, Gdansk (PL); Bartosz Dunajski, Gdansk (PL); Ben Ashbaugh, Folsom, CA (US); and Brandon Fliflet, El Dorado Hills, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 1, 2022, as Appl. No. 17/978,426.
Application 17/978,426 is a continuation of application No. 16/951,217, filed on Nov. 18, 2020.
Prior Publication US 2023/0051227 A1, Feb. 16, 2023
Int. Cl. G06T 1/60 (2006.01); G06F 3/06 (2006.01); G06T 1/20 (2006.01)
CPC G06T 1/60 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a package assembly comprising a plurality of distinct chiplets and a plurality of interconnect structures, the plurality of distinct chiplets including:
a first chiplet comprising:
a first semiconductor die including a first high-bandwidth memory (HBM) device; and
a second semiconductor die including a second HBM device; and
a second chiplet comprising:
a third semiconductor die coupled with the first semiconductor die and the second semiconductor die in a 2.5-dimensional (2.5D) arrangement, the third semiconductor die including a graphics processing resource and a cache coupled with the graphics processing resource, wherein,
the cache is configured to cache data associated with memory accessed by the graphics processing resource, and
the graphics processing resource includes a general-purpose graphics processor core and a tensor core.