US 12,217,175 B2
Methods and apparatus to conditionally activate a big core in a computing system
Rajesh Poornachandran, Portland, OR (US); and Vincent Zimmer, Issaquah, WA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/560,025.
Claims priority of provisional application 63/222,938, filed on Jul. 16, 2021.
Prior Publication US 2022/0113978 A1, Apr. 14, 2022
Int. Cl. G06F 9/46 (2006.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 21/54 (2013.01); G06N 3/042 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/08 (2013.01) [G06F 9/3877 (2013.01); G06F 9/455 (2013.01); G06F 9/45508 (2013.01); G06F 9/4856 (2013.01); G06F 9/5044 (2013.01); G06F 9/505 (2013.01); G06F 9/5066 (2013.01); G06F 21/54 (2013.01); G06N 3/042 (2023.01); G06N 3/063 (2013.01); G06F 2209/501 (2013.01); G06F 2209/5017 (2013.01); G06F 2209/503 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus to conditionally activate a big core in a computing system, the apparatus comprising:
first instructions in the apparatus; and
processor circuitry to execute the first instructions to:
in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing second instructions according to the request;
when the two or more processing devices are available and capable of executing the second instructions:
split the second instructions into first sub-instructions and second sub-instructions;
provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and
generate an output for the second instructions by combining a first output of the first processing device and a second output of the second processing device.