US 12,217,165 B2
Concurrent write and verify operations in an analog neural memory
Hieu Van Tran, San Jose, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Mar. 2, 2021, as Appl. No. 17/190,376.
Claims priority of provisional application 63/070,051, filed on Aug. 25, 2020.
Prior Publication US 2022/0067499 A1, Mar. 3, 2022
Int. Cl. G11C 16/24 (2006.01); G06N 3/065 (2023.01); G11C 11/40 (2006.01); G11C 16/10 (2006.01); G11C 16/12 (2006.01); G11C 16/26 (2006.01)
CPC G06N 3/065 (2023.01) [G11C 11/40 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An analog neural memory system comprising:
a first bank comprising a first array of non-volatile memory cells;
a second bank comprising a second array of non-volatile memory cells;
writing circuitry shared by the first bank and the second bank and selectively coupled to the first bank by a first write multiplexor and selectively coupled to the second bank by a second write multiplexor;
sensing circuitry shared by the first bank and the second bank and selectively coupled to the first bank by a first read multiplexor and selectively coupled to the second bank by a second read multiplexor;
a column multiplexor to connect, when enabled, bit lines in the first array to bit lines in the second array to enable control of the first array and the second array as a single array; and
control circuitry for concurrently performing a write operation using the writing circuitry on one of the first bank and the second bank and a verify operation using the sensing circuitry on the other of the first bank and the second bank.