US 12,217,162 B2
Integrated circuit chip apparatus
Shaoli Liu, Beijing (CN); Xinkai Song, Beijing (CN); Bingrui Wang, Beijing (CN); Yao Zhang, Beijing (CN); and Shuai Hu, Beijing (CN)
Assigned to CAMBRICON TECHNOLOGIES CORPORATION LIMITED, Beijing (CN)
Filed by Cambricon Technologies Corporation Limited, Beijing (CN)
Filed on Dec. 20, 2022, as Appl. No. 18/085,273.
Application 18/085,273 is a continuation of application No. 16/721,875, filed on Dec. 19, 2019, granted, now 11,562,216.
Application 16/721,875 is a continuation of application No. PCT/CN2019/073453, filed on Jan. 28, 2019.
Claims priority of application No. 201711343642.1 (CN), filed on Dec. 14, 2017; application No. 201711346333.X (CN), filed on Dec. 14, 2017; application No. 201711347310.0 (CN), filed on Dec. 14, 2017; application No. 201711347406.7 (CN), filed on Dec. 14, 2017; application No. 201711347407.1 (CN), filed on Dec. 14, 2017; application No. 201711347408.6 (CN), filed on Dec. 14, 2017; and application No. 201711347767.1 (CN), filed on Dec. 14, 2017.
Prior Publication US 2023/0120704 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06F 17/15 (2006.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G06N 3/06 (2006.01); G06N 3/08 (2023.01); H01L 25/065 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/483 (2013.01); G06F 7/5443 (2013.01); G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/06 (2013.01); G06N 3/08 (2013.01); H01L 25/065 (2013.01); G06F 2207/4824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit chip apparatus comprising: a main processing circuit and a plurality of basic processing circuits, wherein
the plurality of basic processing circuits are configured to perform a first set of neural network computations in parallel on data transferred by the main processing circuit to obtain a plurality of computation results, and transfer the plurality of computation results to the main processing circuit, and
the main processing circuit is configured to perform a second set of neural network computations in series on the plurality of computation results.