US 12,217,159 B2
Fault tolerant artificial neural network computation in deep learning accelerator having integrated random access memory
Poorna Kale, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 6, 2020, as Appl. No. 16/987,123.
Prior Publication US 2022/0044102 A1, Feb. 10, 2022
Int. Cl. G06N 3/063 (2023.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 17/16 (2006.01); G06F 30/27 (2020.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 9/3004 (2013.01); G06F 9/5027 (2013.01); G06F 17/16 (2013.01); G06F 30/27 (2020.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
reading, from a portion of random access memory of a device, fourth data during executing of instructions to generate a first output of an artificial neural network based on first data representative of parameters of the artificial neural network, second data representative of the instructions, and third data representative of an input to the artificial neural network;
applying random bit errors, generated to simulate compromised or corrupted memory cells in the portion of the random access memory, to the fourth data to generate a second output of the artificial neural network responsive to the third data stored in the random access memory, wherein the random bit errors are errors applied to random bits in the fourth data; and
adjusting, based on a difference between the first output and the second output, matrix computations of the artificial neural network to reduce sensitivity to presence of compromised or corrupted memory cells in the portion of the random access memory.